Mangesh Kondalkar
Engineer, Senior Staff/Manager at Qualcomm
- Role
- Senior Staff Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Mangesh Kondalkar
Design Verification Lead | UVM | System-Verilog | Formal Verification | VLSI Expert | AuthorGold Medalist in Electronics Engineering (B.Tech, Mumbai University) and M.Tech in VLSI Design with Distinction (VTU).I bring 11+ years of experience in Design Verification domain with expertise in UVM, System-Verilog, and Advanced Verification Methodologies.Experience in developing complex testbench for IP and Subsystem verification, ensuring robust and high-quality designs. Currently, I lead a team of 5+ DV engineers for an IP used in AI/ML hardware. My responsibilities include planning effort estimates, Testbench strategy to verify new IP features and delivering bug free RTL across multiple projects. Hands on experience in Formal verification tools (JG & VCF) and methodologies like FPV & SEQ. Proven track record in driving Innovation and Quality in DV methodologies. Published papers in internal and external DV forums (DVCon & DTDC).
Experience
Senior Staff Engineer
Dec 2024 — Present · Bengaluru, IN
Education
RV College Of Engineering
Master of Technology (M.Tech.), VLSI Design and Embedded Systems
2012 — 2014
MUMBAI UNIVERSITY
BE, ELECTRONICS
2006 — 2010
Skills
- Embedded C
- Digital Circuit Design
- Vlsi
- Embedded Systems
- System Verilog
- Systemverilog
- Software Development
- Microcontrollers
- Firmware
- Ibm Iseries
- Rpg
- Arm
- C++ Language
- Mainframe
- Verilog
- Vhdl
- Systemc
- Fpga
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