Mandar Joshi

About Mandar Joshi

Delivered 12 successful tape-outs through 13 years of experience in Physical Design with background in RTL Design- Full-stack Physical Design: Proficient in all aspects of the physical design flow, including block and top-level implementation, flow/methodology development, and automation- Leadership & Team Management: Led a team responsible for the successful synthesis to GDS delivery of 8 multi-instantiated blocks- Cross-functional Collaboration: Worked closely with RTL, Analog, and Firmware teams to achieve optimal design closure, including low-power techniques (UPF, distributed power gating), PnR-friendly RTL development, and integration of analog IPs (DDR PHY IP)- Foundry Expertise: Delivered designs to tapeout across multiple foundries and nodes (Intel 14, 10, 7; Global Foundries 28, 22; TSMC 40, 16, 7, 6)- Technical Proficiency: Fluent in Synopsys and Cadence P&R tool chains. Strong scripting skills in TCL, Python, and Shell- Gained valuable experience across a range of environments, including dynamic startups and established IP development teams.

Experience

1. Cpu Design Engineer

   Apple

   Nov 2025 — Present · Santa Clara, CA, US

Education

• VES Institute of Technology

  B. E., Electronics Engineering

  2006 — 2010

• San José State University

  Master of Science, Electrical Engineering

  2011 — 2013

Skills

• Modelsim
• Digital Circuit Design
• Embedded Systems
• Power Management
• Fpga
• Asic
• Logic Synthesis
• Microcontrollers
• Rtl Design
• Digital Ic Design
• C
• Static Timing Analysis
• Vlsi
• Integrated Circuit Design
• Microprocessors
• Verilog
• Spyglass
• Python