Mandar Patil

About Mandar Patil

20+ years in ASIC Design Verification and validation.# Core expertise in Test-plan generation, Test-bench development in systemverilog using UVM methodology, Module level and chip level tests development, code coverage and familiar with functional coverage, Board bring-up and features validation.# Knowledge of Ethernet protocol 802.3, 40G /100G ethernet 803.ba, EPON 802.3ah, OTN G709. MIPI CSI 2 Amba lite - Arm Cortex M3# familiar with TCP/IP, MIPS subsystem, SSL protocol

Experience

1. Senior Principal Engineer

   Marvell Technology

   Apr 2023 — Present

Education

• Dr.Babasaheb Ambedkar Technological University, Lonere - Raigad

  B.TECH, Electronics and Telecommunication

  1996 — 1999

• swami Vivekanad Education Polytechnic,chembur

  diploma in enginerring, Elelctronics and Telecommunication

  1994 — 1996

Skills

• Vmm
• Application-Specific Integrated Circuits (Asic)
• Optical Transport Network (Otn)
• Soc
• Gigabit Ethernet
• Uvm /Vmm
• Tcl
• Field-Programmable Gate Arrays (Fpga)
• Rtl Coding
• Verilog
• Microprocessors
• Fpga
• Asic
• Processors
• Ethernet
• Semiconductors
• Modelsim
• Very-Large-Scale Integration (Vlsi)
• Formal Verification
• Otn
• System on a Chip (Soc)
• Vlsi
• Debugging
• Logic Synthesis
• Systemverilog
• Validation
• Universal Verification Methodology (Uvm)
• Uvm
• Functional Verification
• Open Verification Methodology
• Ncsim
• Board Bring-Up
• Rtl Design