Manas Kanithahalli Sadananda
SOC Debug Engineer | DFD, Debug Architecture, Debug Tools
- Role
- Soc Debug Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Manas Kanithahalli Sadananda
Platform Debug Engineer with over three years in post-silicon validation, specializing in…
Experience
Soc Debug Engineer
Apr 2022 — Present · Hillsboro, OR, US
Education
Portland State University
Master's degree, Computer Architecture
2012 — 2014
BMS Institute of Technology
Bachelor of Engineering (B.E.), Electronics and Communication
2004 — 2008
Skills
- Simulink
- Vivado
- Soc
- Modelsim
- Matlab
- Orcad Capture
- Usb
- Xilinx
- Systemverilog
- Python
- Latex
- Autocad
- Algorithms
- Electronics
- Application-Specific Integrated Circuits (Asic)
- Simplescalar
- Embedded C
- Perl
- Embedded Systems
- Computer Architecture
- Debugging
- Microprocessors
- Systemverilog Assertions
- Rtl Design
- Hardware Architecture
- Chipscope
- C
- Fpga
- Asic
- Vhdl
- Simulations
- Static Timing Analysis
- Baan
- Xilinx Ise
- Pcb Design
- Verilog
- C++
- Microcontrollers
- Field-Programmable Gate Arrays (Fpga)
- Mplab
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.