Manasa T S R
- Role
- Senior Design Engineer (Dft) at Samsung Electronics
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Manasa T S R
I am a Straightforward and dependable individual with strong interest to learn and innovate on the Research and development side of Semiconductor VLSI Design.Currently, I am advancing my expertise in System On Chip (SOC) Design, worked on the GPU and CPU cores Verification from SOC level with post silicon debug and Support for multiple Chip-tape outs.Worked on the design Verification of DFT and Block level ATPG, Spyglass, MBIST for Timing and No-Timing Simulations for SSN Architecture.
Experience
Senior Design Engineer (Dft)
Aug 2022 — Present · Bengaluru, IN
Education
Narayana Junior College , Hyderabad
Board of Intermediate Education
2014 — 2016
Amrita Vishwa Vidyapeetham
Bachelor of Technology - BTech
2016 — 2020
D.A.V. Public School - Hyderabad
CBSE
2014 — 2014
National Institute of Technology Calicut
Master of Technology - MTech
2020 — 2022
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