Manasa B S

About Manasa B S

M.Tech graduate in VLSI Design from Manipal University with hands-on experience in verifying a multi-channel DMA IP as part of a year-long internship at AMD India.During my internship, I developed UVM-based testbenches, authored SystemVerilog assertions for protocol checks, and achieved >95% functional and code coverage. I automated log parsing and regression flows using scripting (Perl, SHELL), and debugged simulation failures using Verdi and waveform analysis. This experience gave me deep exposure to AXI protocol, Synopsys VCS, and Unix-based flows, while also building collaboration skills with integration and DV teams.I recently presented a literature review paper on low-power clock gating techniques at the ICMREST 2025 conference, showcasing my ability to bridge academic concepts with real-world design challenges.Currently seeking a full-time Design Verification Engineer role where I can contribute to high-quality IP/SoC verification, push coverage closure, and continue growing in constrained-random, assertions, and automation.Let’s connect if you’re hiring or looking to collaborate in the VLSI/semiconductor space.

Experience

1. Silicon Design Engineer 2

   AMD

   Jan 2026 — Present · Bengaluru, IN

Education

• Evershine english school

  10th Std

• Manipal Institute of Technology

  Postgraduate Degree, Microelectronics

• Jnanodaya pu college

  Puc, Pcmb

• Global Academy Of Technology

  Bachelor of Engineering - BE, Electronics and communication