Mamta Rana
Cadence
San Jose, CA, US
EMAILS
MOBILE NUMBERS
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WORK HISTORY
Present
@Cadence
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SKILLS
SocModelsimCadence VirtuosoXilinxSystemverilogQuestaVlsiFormal VerificationVeritas Cluster ServerSystem on a Chip (Soc)Universal Verification Methodology (Uvm)Application-Specific Integrated Circuits (Asic)Field-Programmable Gate Arrays (Fpga)Rtl CodingUvmOpen Verification MethodologyPhysical DesignNcsimAxiEdaStatic Timing AnalysisDigital ElectronicsLogic DesignRtl DesignAmba AhbFunctional VerificationVery-Large-Scale Integration (Vlsi)FpgaVerilogAsicSemiconductorsLogic SynthesisIntegrated Circuit DesignTclVmmVhdlSimulations
ABOUT MAMTA RANA
Senior Engineering Manager with 15+ years of experience in semiconductor design and…
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