Mallikarjunarao Thummalapalli

About Mallikarjunarao Thummalapalli

My professional experience in the industry is 10 years.In that 7+ years of experience in DFT and 3 years of experience in ASIC Verification.Professional Skills & Pattern generation for SCAN and RAMBIST•Coverage Analysis for blocks of <99% and SoC level.•Simulations (No-Timing and Timing) for SCAN (Block, Macromap and SoC level) and RAMBIST, Debug for simulation failures.•DCSU based simulations @ SoC level.•SoC level activities of JTAG Testing (BSDL), Inter Connect Test and IDDq.•Support for Silicon bring-up activities and Debug for simulation failures.•Worked on RMA issues by using ET Diagnostics tool to identify the faulty node.**Flow developed for SoC DFT Hook-up connectivity checks @ RTL level using Assertions and the same concept delivered as a paper in CDNLive 2015.**Flow developed for JTAG Testing @ RTL level•Knowledge of Digital Circuit Design, Verilog HDL and System Verilog Coding.•Scripting language Makefile Based scripting, shell commands and Perl command.•SVN Vault and LSF knowledge.•Tools EncounterTest, NCSIM, Rocketick and ET Diagnostics.

Experience

1. Principal Dft Engineer

   Marvell Technology

   Nov 2024 — Present

Education

• Manipal Academy of Higher Education

  MS, VLSI

  2006 — 2008

• Bapatla Engineering College

  B.Tech, EEE

  2002 — 2006

Skills

• Static Timing Analysis
• Vlsi
• Specman
• Rtl Design
• Ncsim
• Modelsim
• Systemverilog
• Verilog
• Amba Ahb
• Application-Specific Integrated Circuits (Asic)
• Asic
• Eda
• Open Verification Methodology
• Functional Verification