Mallikarjun Shidnal

About Mallikarjun Shidnal

BE, MS in VLSI with 19+ years of Server SOC, ASIC, Microprocessor PD including cutting edge tech. 22nm, 14nm, 6nm, 3nm• 7+ years of Manager / Lead experience in Microchip, IBM, KarMic(client TI) of 5-30 team members.• Experienced in all aspects of RTL to GDS flow across hierarchy IP intensive multimillion gate designs• Managing and Leading full chip (20-40 mm^2) RTL-GDS teams for 32 bit Microcontroller design.• Worked experience in physical design (Full chip IO placement, floor planning, CTS, place & route, DFM, ECO and SI), Physical verification(Calibre / Assura)• Worked on Synopsys ICC and Cadence Encounter across nodes for multiple tape-outs.• Experienced in low power design using UPF flow, Synthesis and Static Timing Analysis.• Experienced in Power, IR drop, EM Analysis using Redhawk.• Expert in PERL and Tcl scripting and methodology development/ support.• Possess excellent leadership and communication skills, and experienced in working with global teams across US and Germany.• Good understanding of low power techniques, RTL coding, DFT• Expertise in standard cell libraries dev.(Schematic, Layout Arch, Layout, Characterization etc.)• Developed and Support of P&R flow (SOC encounter tool) for Standard Cell Library, Design teams.

Experience

1. Senior Manager Design Engineering

   AMD

   Jul 2025 — Present · Bengaluru, IN

Education

• M.S.Ramaiah School Of Advance Studies, Bangalore

  M.S.(Engg), VLSI System Design

  2010 — 2013

• KLE CET Belgaum

  B.E, Electronics and Communication

  2002 — 2006

Skills

• Signal Integrity
• Eda
• Physical Verification
• Rtl Design
• Logic Synthesis
• Timing
• Asic
• Systemverilog
• Verilog
• Cmos
• Timing Closure
• Place & Route
• Soc
• Static Timing Analysis
• Lvs
• Integrated Circuit Design
• Microprocessors
• Functional Verification
• Cadence Virtuoso
• Drc
• Vlsi
• Physical Design
• Tcl
• Clock Tree Synthesis
• Standard Cell