Mallika Rathore

About Mallika Rathore

Hardware Engineer at Google with focus on low power design optimizations and methodologies, pre and post-Si power analysis and correlations.Past experiences- PhD (20••••21): Low voltage DNN accelerator designs exploring the impact of low voltage operation on DNN accuracy. Developed a methodology to quantify the design trade-offs and enable an error-aware low voltage DNN hardware design[Google scholar link - & hl=en]- Timing Engineer at Marvell Semiconductors: Timing closure, constraint analysis.

Experience

1. Hardware Engineer

   Google

   Jul 2021 — Present

Education

• Stony Brook University

  Doctor of Philosophy (Ph.D.), Electrical Engineering

  2016 — 2021

• Stony Brook University

  Master of Science (M.S.), Electrical and Electronics Engineering

  2012 — 2014

• Rajiv Gandhi Prodyogiki Vishwavidyalaya

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2008 — 2012

Skills

• Verilog
• Pspice
• Rtl Design
• Perl
• Synopsys Platform Architect
• Cadence
• Modelsim
• Analog Circuit Design
• Design Verification Testing
• Altera Quartus
• Circuit Design
• Python
• Latex
• Vbscript
• Logic Synthesis
• Very-Large-Scale Integration (Vlsi)
• Soc
• Eagle Pcb
• C++
• Rtl
• Java
• Spice
• Microsoft Visual Studio C++
• System on a Chip (Soc)
• Application-Specific Integrated Circuits (Asic)
• System Architecture
• Ltspice
• Xilinx Ise
• Matlab
• Low-Power Design
• Sta
• Systemc
• Hspice
• Fpga
• Asic
• Semiconductors
• Cadence Virtuoso
• Vlsi
• Physical Design
• Orcad Capture Cis