Malli Chilakala

Experience

1. Networking Software Architect and Senior Member of Technical Staff

   Intel

   Feb 2017 — Present

   Senior Member of technical Staff lead/SW architect responsible for 1st Generation IOTG TSN SW Full stack Linux solutions on Intel’s MAC controller on Intel Industrial automation IOT (Internet of Things) platforms. Innovated optimized latency bounded deterministic performance Ethernet XDP-ZC drivers (eXpress Data Path, Zero Copy), SDN (Software Defined Networks) ONF/OpenFlow SmartNIC offloading capabilities on Intel MAC controller based discrete and integrated MAC based platforms. Architected, led SW implementation of 1st Gen TSN key differentiation technologies on discrete Intel MAC controller and integrated MAC controller on several Intel SoC platforms. Drove and implemented Linux SW core offloading features, E2E TSN solutions with 802.1AS gPTP (Precision Time Protocol), 802.1Qav/Qbv CBS (Credit Based Shaping)/AVB (Audio Video Bridging), TBS (Time Based Scheduling) Launch time ETF Earliest Tx-Time First, TAPRIO (Time aware priority scheduling) and 802.1Qbu Frame preemption protocols. Delivered extremely optimized RT Time Deterministic offerings for the 1st time on Intel discrete and integrated MAC controllers on Intel IA platforms. Led architecture and implementation of optimized latency bounded deterministic Edge Connected Solutions with XDP-ZC on Intel discrete and integrated ethernet MAC controller. Steered strategic direction of the implementation, optimized E2E KPI cycle-time latencies for industrial use-cases. Drove DPDK stack-less changes on Intel i225 1G and 10G MAC controllers for use-spaced application-based Device Queue (ADQ) for low-latency use-cases.