Mallesh Balla
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Mallesh Balla
DFT:* Good experience on block and SOC level test pattern generation for SAF and TDF…
Experience
Sr Silicon Design Engineer
Mar 2020 — Present
ATPG simulations
Skills
- C
- Joint Test Action Group (Jtag)
- Bash
- Digital Electronics
- Perl
- C++
- Scan
- Vhdl
- Verilog
- Shell Scripting
- Automatic Test Pattern Generation (Atpg)
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