Vamsee Mohan Mallela
IP Logic Design Engineer at Intel Corporation
- Role
- Ip Logic Design Engineer at Intel
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Vamsee Mohan Mallela
Expertise in Design, Layout and Validation of High Efficiency Standard Cell, I/Os, SRAM…
Experience
Ip Logic Design Engineer
Oct 2024 — Present · Hyderabad, IN
Education
California State University-Sacramento
Master of Science
2009 — 2011
Sant Samarth Engineering College
Bachelor of Technology
2005 — 2009
Kendriya Vidyalaya Picket, Secunderabad
Class 12th
1993 — 2005
Skills
- Cadence Virtuoso
- Fpga
- Asic
- Field-Programmable Gate Arrays (Fpga)
- Static Timing Analysis
- Digital Electronics
- Vlsi
- Synopsys Tools
- Verilog
- Pspice
- Modelsim
- Cadence
- Ic
- Pcie
- Xilinx
- Systemverilog
- Cmos
- Debugging
- Rtl Design
- Cad
- Vhdl
- Simulations
- Spice
- Tcl
- Logic Analyzer
- Mixed Signal
- Circuit Design
- Layout
- Computer Architecture
- Soc
- Digital Signal Processors
- Analog Circuit Design
- System on a Chip (Soc)
- Xilinx Ise
- Oscilloscope
- Pcb Design
- Hardware Architecture
- Functional Verification
- Logic Design
- Integrated Circuit Design
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