Malini Ramapura

About Malini Ramapura

I am a graduate student at The University of Texas at Dallas seeking full time opportunity in the field of VLSI design and Verification. Worked in Wipro Technologies from May 2011 to March 2013 as VLSI verification Engineer. Worked on front end verification in VMM system verilog Environment.Technical Skills:• Full custom ASIC Design flow and Verification,FPGA, RTL verification, Static Timing Analysis• Programming Languages : C, C++, MATLAB, Assembly Language (x86)• HDL/Scripting Languages :Verilog and basic VHDL, Perl• System Verilog :VMM Verification Methodology • CAD Tools :Synopsys- Design Vision, Primetime, TetraMax, Liberty NCX : Cadence-Virtuoso, Composer Schematic editor, Encounter• Software packages : ModelSim, MultiSim, Xilinx ISE, AWR VSS

Experience

1. Mts Silicon Design Engineer

   AMD

   Jan 2022 — Present · Fort Collins, CO, US

   Fort Collins, Colorado, United States

Education

• The University of Texas at Dallas

  Master's Degree

  2014 — 2015

• SIT , Tumkur

  Bachelor of Engineering (B.E.)

  2007 — 2011

Skills

• Vhdl
• Cplex
• Cadence
• Verilog
• Functional Verification
• Clock Tree Synthesis
• Rtl Verification
• Perl
• Physical Design
• Synopsys Primetime
• Layout
• Systemverilog
• Xilinx Ise
• Static Timing Analysis
• Tetramax
• Rtl Design
• Modelsim
• Place & Route
• Vlsi
• Dft
• Unix
• C++
• Hdl Verification
• Cadence Virtuoso
• Fpga
• Asic
• Rtl Coding
• Hvl
• Cadence Encounter
• C