Malay Trivedi

About Malay Trivedi

Senior Principal Engineer at Intel in the Network and Edge Group (NEX). System-on-Chip (SoC) Lead Architect with strong technical background in multiple CPU architectures (x86, ARM, RISC-V). Responsibilities include product feature pathfinding, SoC architecture definition and close collaboration with Design Engineering and System Verification teams towards product tape-in and production. I am passionate about developing innovative and competitive products, leveraging experience that spans System, SoC, chiplets, IO and Peripherals Architecture/Micro-Architecture.

Experience

1. Senior Principal Product Architect

   SiFive

   Mar 2025 — Present

Education

• University of Wisconsin-Madison

  MS, Electrical Enginering

  1994 — 1996

• Indian Institute of Technology, Bombay

  B.Tech., Electrical Enginering

  1990 — 1994

• University of Illinois Chicago

  Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering

  1996 — 2001

• Kendriya Vidyalaya

  High School

  1978 — 1988

Skills

• Physical Design
• Cadence Virtuoso
• Vlsi
• Processors
• Cmos
• Integrated Circuits (Ic)
• Digital Signal Processors
• Analog Circuit Design
• Ic
• Fpga
• Asic
• Pll
• Timing Closure
• Pcie
• Verilog
• Rtl Design
• Semiconductors
• Integrated Circuit Design
• Microprocessors
• Static Timing Analysis
• Systemverilog
• Debugging
• Eda
• Hardware Architecture
• Soc
• Functional Verification
• System on a Chip (Soc)
• Mixed Signal
• Circuit Design
• Signal Integrity
• Dft
• Low-Power Design
• Field-Programmable Gate Arrays (Fpga)
• Power Management
• Application-Specific Integrated Circuits (Asic)
• Logic Design
• Analog