Majid Shushtarian

About Majid Shushtarian

Current focus in System Secure Boot and Patch and Power Management and Security assurance on XEON Server Platform and AI Accelerator Systems. Enabling Vendor authorized Secure Boot and @scale Debug. Platform Security Threat Model generation and Security analysis of XEON Server and AI Accelerator Systems. Perform Security Penetration Testing on the Xeon Server and AI Accelerator Systems.Background: 30+ years of Servers and AI Accelerator System Architecture, X86 Secure Boot/Reset and Power Management and Thermal Architecture of Servers, and Client Systems. Technical Design Management and Design and Development of SOCs, ASICs, Audio CODECs and Digital Signal Processing, proof of concept and software integration on FPGAs, AMBA bridge design and Tensilica and ARM processor integration, Embedded Controllers, LAN, DRAM interface, Airbag controllers, Southbridge chipsets and X86 Intel CPU design.Areas of expertise: Server and Client System Secure Boot and Patch and Power Management and Security assurance. Management and Design implementation from Product and Architecture definition, design and test to production. Matlab analysis, RTL coding and verification, synthesis, timing analysis, silicon debug in lab and on tester.Self starter, motivator, team player with cross functional and remote teams. Customer Interface with major OEMs and IP evaluation. Contributor to MIPI Battery and Sensor Interface Standard groups. Three US patents in the areas of Server Systems, Audio Speaker protection and Mobile Haptics.

Experience

1. System and Security Architect of Xeon Servers and Ai Accelerators

   Intel

   Jul 2014 — Present · Santa Clara County, CA, US

   System Secure Boot and Patch and Power Management and Security assurance of XEON Server and AI Accelerator Systems. Enabling Vendor Authorized Secure Boot and @scale Debug. Platform Security Model generation and Security analysis of XEON Server Systems. Perform Security Penetration Testing on the Xeon Server Systems.

Education

• San José State University

  M.S., Electrical Engineering

  1992 — 1994

• San José State University

  MBA, Business

  1998 — 2000

• San Francisco State University

  B.S., Electrical Engineering with Minor in Computer Science

  1985 — 1989

Skills

• Fpga
• Asic
• Pll
• Semiconductor Industry
• Customer Engagement
• Static Timing Analysis
• Envelope Tracking for Power Rf Amplifier
• Debugging
• System Architecture
• Silicon
• Mixed Signal
• Circuit Design
• Audio Speaker Protection
• Ip Evaluation
• Soc
• Digital Signal Processors
• Analog Circuit Design
• Linear Resonant Actuator Haptic Driver
• Matlab to Verilog
• Integrated Circuit Design
• Microprocessors
• Analog
• Power Management
• Processors
• Cmos
• Semiconductors
• Sensor Hub
• Sensors
• Functional Verification
• Hardware Architecture
• Rtl Design
• Audio Codecs
• Verilog
• Low-Power Design
• Dft Algorithms
• Ic
• Dsp
• Cadence Virtuoso
• Serdes
• Vlsi