Mahipal Routhu

About Mahipal Routhu

Analog Mixed-Signal Layout Engineer with 8+ years of experience in building layouts for high-speed clocks, power delivery R&D cells, analog blocks in PCIe7, PCIe6, DDR5IO, Gen3 Serdes, GPIO and Preamp.My role is to construct layouts from hierarchical sub-blocks to top-level CBBs and macros, from floor planning to tape-out. Which includes area estimation, floor planning, pin placement, LEF, matching placements and routings, power grid generation, top-level routings for analog blocks, fixing ECOs from simulations and feedback from DE, reliability verification (RV violations), and fixing all physical verifications such as DRC, LVS, and DFM, as well as parasitic extractions, to achieve high-quality layout deliveries. PROFILE HIGHLIGHTS:8+ years of hands-on experience in custom layout design from sub-block to block level, from circuit schematicsDelivering CBBs and macros within the timeline with speed and qualityI worked in different process GAAFET, Nanosheets, FINFET, CMOS. Tech nodes like TSMC(2nm, 3nm, 5nm, 6nm), Intel-(7nm, 10nm, 22nm), TSMC-45nm and 130nm.Experienced in the layout design of analog blocks such as Op-Amp, ADC, RX, CM_ana, Deksew, RX-bias, SCVR, LDO, DFE, level shifters, standard cells, etc.Delivered LEF, PIN placement, RV, and LV signoff clean layout databases for various milestones as per the client\'s requirements, within the timeline.I\'m proficient in floorplans and routing symmetry, mainly to minimise the routing complexity and delays.Usage of modgens and cloning methods to make effective use of time during placement and routing.Strong knowledge in analysing and solving EM, SH, FISH, IR Drop, reliability verification issues.In-depth knowledge of EDA tools: Cadence Virtuoso Layout Editor, ICV Synopsys, Intel Genesys, Calibre, Totem, and Tavor.Expert in verification checks in lower nm, like LVS, DRC, ERC, MRC, density issues, and DFM rules.Experience in understanding and using different solving methods for the antenna effect.Knowledge of latch-up and being good at fixing latch-up related issues and LEF issuesUnderstanding of mask layers (device ids) and double/triple patterns in layout and their issues in doing layout.A strong team player with good communication skills for working with engineers spread across the globe and sites.

Experience

1. Staff Engineer

   Synopsys Inc

   Oct 2024 — Present · Hyderabad, IN

Education

• C-DAC ACTS Pune

  PG Diploma, VLSI Design

  2017

• Jyothishmathi institute of technology and science

  B.Tech (Bachelor of Technology), Electronics and Communication Engineering

  2012 — 2016

• S V Junior College

  Inter (+2), MPC

  2010 — 2012

• Siddartha High School

  SSC, General Studies

  2001 — 2010