Mahima Bhatnagar

About Mahima Bhatnagar

Executive Summary: A highly motivated and results-oriented Product Validation Engineer with four years of experience in the semiconductor industry. Proven ability to perform thorough pre-silicon verification using industry-standard methodologies and tools. Skilled in hardware languages (SystemVerilog), verification methodologies (UVM) and simulation tools (Synopsys VCS, Verdi, Venus). Key Highlights- Working as a Product Validation Engineer II at Cadence Design Systems - Intel Technology India Pvt. Ltd: Performed pre-silicon validation on DFD domain for Trace fabric for Xeon servers, achieving 99% toggle coverage. Collaborated with various teams for efficient debugging and bug identification- Wipro Technologies: Supported pre-silicon validation of Intel\'s client SoCs, specializing in the LNL variant. Developed and improved test cases and actively participated in debug. Technical Skills- Hardware Languages: Verilog, SystemVerilog - Verification Methodology: UVM - Scripting Languages: Python - Simulation Tools: Synopsys VCS, Verdi, Venus, ModelSim - Operating Systems: Linux, Windows

Experience

1. Pre-silicon Validation Engineer

   Intel

   Jan 2023 — Present · Bengaluru, IN

   Designation: Pre-Si Validation Engineer- Performed pre-silicon functional verification of Design for Debug (DFD) domain for Xeon server in the Trace and VISA fabric for the CWF project- Perform verification of the DFD design, validating its functional characteristics and identifying potential design flaws or bugs- Leveraged both simulation and emulation environments to comprehensively test the functionality and use cases of various DFD fabrics- Collaborated effectively with SoC architects, RTL developers, and the post-silicon team to pinpoint and resolve RTL bugs, streamlining the debugging process- Developed a comprehensive test case and corresponding verification tests aligned with project requirements- Executed test case, validated test results, and performed debug activities using the Universal Verification Methodology (UVM)- Continuously learn from post-silicon validation results to improve the quality of pre-silicon verification processes, ensuring these improvements are incorporated into future product development- Demonstrated expertise in industry-standard tools by proficiently using Synopsys VCS, Verdi, and Venus tools for simulation, debugging, and analysis tasks.

Education

• SIR PADAMPAT SINGHANIA UNIVERSITY UDAIPUR

  Bachelor of Technology (BTech)

  2013 — 2017

• Vellore Institute of Technology

  M.Tech

  2019 — 2021