Mahesh Bhat K

About Mahesh Bhat K

Working as a SoC Physical Design Engineer at Apple since May 2023. With internship experience at Apple and Nvidia.Completed my Masters in Electrical Engineering with focus on VLSI Design with GPA of 4.0 at University of Southern California, Los Angeles.Completed my Bachelors in Electronics and Communication Engineering with GPA of 9.33/10 at R.V.College of Engineering, Bangalore, India.Languages: HDL - Verilog, Python, C, TCL.Tools: Xilinx Vivado, Cadence Virtuoso, Cadence Innovus, ICC2, RedHawk, ModelSim/Questasim, Intel Quartus Prime, OpenLane, CppSim, ngSpice, Yosys.Worked on DE1-SoC FPGA Cyclone V Board, Arduino and Raspberry Pi.Major Subjects: Digital VLSI Design, Designing with Verilog, Low Power VLSI Design, VLSI Algorithms and Automation, VLSI Testing for IC, Computer Systems Organization, MOS VLSI Circuit Design, Computer Systems Architecture, VLSI System Design.Other activities engaged in include photography, travelling, hiking, football, cricket, F1.

Experience

1. Soc Physical Design Engineer

   Apple

   May 2023 — Present · Beaverton, OR, US

   SoC Partition PnR Implementation & Closure(including STA, PDV, IR and others), Analysis & Design tools development, IP core Pushdown : FloorPlanning, Feedthrough planning & Pin planning.

Education

• Sri Vidya Mandir Education Society

  High School , SSLC

  2014 — 2015

• Vidya Mandir IND PU College

  Pre University , PCME

  2015 — 2017

• University of Southern California

  Masters, Electrical Engineering

• RV College Of Engineering

  BE - Bachelor of Engineering, Electronics and Communications Engineering