Mahesh Uppala
Design Verification Engineer
- Role
- Design Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Jan 2025 — Present · Bengaluru, IN
S3M (Security Startup Service Module) Firmware Verification Engineer, specializing in OVM-based SystemVerilog testbenches and test sequences, with automation using Python, Perl, and Bash in a pre-silicon validation environment.
Education
Visvesvaraya National Institute of Technology
Master of Technology - MTech
Osmania University
Bachelor of Engineering - BE, Electronics and communication engineering
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