Mahesh Reddy
Engineer @ Cadence Design Systems
- Role
- Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Mahesh Reddy
Verification Engineer with 2+ years of experience working on block-level verification. Skilled in SystemVerilog, UVM, low-power (UPF) verification, simulation debug, regression analysis, and coverage closure. Hands-on experience in debugging UVM testbench environments, triaging large regressions, analyzing functional and code coverage, validating power intent, and improving verification efficiency through automation.I enjoy solving complex verification challenges, optimizing debug workflows, and collaborating across teams to deliver high-quality silicon. Actively seeking opportunities in Design / SoC Verification to grow and contribute to cutting-edge semiconductor development.
Experience
Engineer
Jan 2024 — Present · Bengaluru, IN
Education
Guru Nanak Institutions(GNI)
Bachelor of Technology - BTech, ECE
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech, VLSI design & Microelectronics
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