Mahesh M
FPGA RTL Design and Verification Engineer
- Role
- Llm Hardware Engineer at Turing
- Location
- Kolar, KA, IN
- LinkedIn followers
- 500 followers
About Mahesh M
Electronic has been a part of my childhood curiosities and aspirations. I started off with things like motors, dynamos, I love to create things from scratch and i thoroughly enjoy the process. As part of My technical strength my offerings to the industries are : verilog code coverage synthesis RTl coding FSM based design Digital electronics Digital design Linux and much more.
Experience
Llm Hardware Engineer
Jun 2024 — Present · US
Creating RTL Verilog data points for training a large language model.
Education
Government polytechnic college kgf
Electronic and communication
Visvesvaraya Technological University
Bachelor of Engineering - BE, Electronics and communication
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