Mahesh Kumar M

About Mahesh Kumar M

I am DFT Engineer with 6 years of experience in developing and optimizing DFT methodologies for ASIC SoC designs. My expertise spans the entire DFT cycle, from RTL-level rule checks to ATPG pattern generation and silicon validation, ensuring high test coverage and manufacturability.I have worked on multiple customer engagements with leading semiconductor companies helping them evaluate and implement DFT solutions into their workflows.My hands-on experience includes- DFT Flow Development - Scan Compression, OCC insertion and scan stitching using Synopsys DC/FC- ATPG and coverage analysis for stuck-at, transition delay fault models- Scan pattern validation - Pre/post-DFT DRC analysis and pattern validation using Synopsys VCS- Customer collaboration and Support - Driving post-sales support and silicon testability enhancements.

Experience

1. Staff Engineer

   新思科技股份有限公司

   Feb 2025 — Present · Bengaluru, IN

   Key Responsibilities include- Worked with Semiconductor industry leaders to evaluate and deploy Synopsys DFT solutions- Performed DFT rule checks, coverage estimation and connectivity validation using TestMAX Advisor(Spyglass)- Implementing DFT solutions at RTl and gate level designs using TMM and DC/FC- Developing ATPG flow for stuck-at and transition ATPG fault models using TestMAX ATPG- Scan pattern validation using Synopsys VCS across various PVT corners- Assisted customers in integrating Synopsys DFT flow in their environments, providing post-sales support.

Education

• Brindavan College of Engg., BANGALORE

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

  2011 — 2015

• Kendriya vidyalaya crpf, yelahanka

  12

  2010 — 2011