Mahesh Borgaonkar
Packaging R&D Engineer at Intel Corporation
- Role
- Packaging R & d Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Mahesh Borgaonkar
Experienced Product Designing Engineer doing the designs for technologies such…
Experience
Packaging R & d Engineer
Jul 2020 — Present · Bengaluru, IN
Education
Portland State University
Masters
2011 — 2013
Nagpur University
Bachelors
2005 — 2009
University of Pune
Diploma in VLSI
2009 — 2010
Skills
- Verilog
- Cadence Virtuoso
- Microsoft Office
- Computer Architecture
- Rtl Coding
- C
- Package Designing
- Electrical Engineering
- Pads Logic
- Cadence
- Knowledge of Substrate Design Rules
- Modelsim
- Cadence Schematic Capture
- Sip
- Vhdl
- Simulations
- Lp Wizard
- Eda
- Systemverilog
- Logic Design
- Xilinx Ise
- Pcb Design
- Pads Layout
- Concept Hdl
- Logic Synthesis
- Dxdesigner
- Microprocessors
- Allegro
- Expedition Pcb
- Fpga
- Asic
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