Mahendran Devarajlu
Design Verification Engineer
- Role
- Asic Verification Engineer at Meta
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Mahendran Devarajlu
18+ years of experience on RTL Design Verification.(SOC and IP) • Have…
Experience
Asic Verification Engineer
Sep 2022 — Present · Austin, TX, US
SOC level verification- experience on chiplet verification. o Verified various function between 4 instances of pcie including inbound, HDMA transactions to various blocks in 4 chiplets. o Verified all real kernels functionality between the chiplets. o Defined and brought up reduced mode configuration for emulation bringup. o Improved soc verification simulation by implementing PCIe reduced mode, fast boot and various log reduction mode. o Mentor interns and junior engineers.• HostIf: o Module connects between pciess and compute module. The module has NOC and other properity blocks.o Developed complete uvm environment from scratch with resuable scoreboard.o Found bug arteris noc during FDH phase.
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