Mahaveer Patil
Technical Director @ACL Digital
San Jose, CA, US
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+91 *********19
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WORK HISTORY
Apr 2023 — Present
Technical Director @ACL Digital
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San Jose, CA, US
Architecture, micro-architecture for RISCV CPU design.High performance out-of-order RISCV CPU, in-order multithreaded multi core configurable RISCV core, microcontroller class CPU.CXL, Clocking architecture, Low power designsLeadership team member for Semiconductor business unit at ACL Digital
EDUCATION
1999 — 2003
Visvesvaraya Technological University
BE, Electronics & Communications
ABOUT MAHAVEER PATIL
Technical Leader and Solution Architect for ASIC/FPGA designs, CPU design, SoC & …
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