Mahananda Maiti
Design and Verification Engineer | Verilog RTL | SystemVerilog & UVM | VLSI Intern @ Maven Silicon | RTL Design & Functional Coverage | B.Tech(ECE) |
- Role
- Vlsi Design and Verification Intern at Maven Silicon
- Location
- Tamluk, WB, IN
- LinkedIn followers
- 500 followers
About Mahananda Maiti
I am a Design Verification Engineer specializing in SystemVerilog and UVM, with a strong foundation in Digital CMOS and RTL Design. I am currently a VLSI Design and Verification Intern at Maven Silicon, where I architect comprehensive testbenches for complex IP blocks to achieve 100% functional coverage.My recent hands-on work includes designing and verifying an APB-based GPIO peripheral and building a highly reusable UVM testbench to verify protocol conversion for an AHB to APB bridge. I am highly proficient in industry-standard EDA tools like Synopsys VCS, QuestaSim, and ModelSim. Core Competencies: SystemVerilog | UVM | Verilog HDL | AMBA Protocols (APB, AHB, AXI)| Functional Verification | Object-Oriented Programming (OOP)
Experience
Vlsi Design and Verification Intern
Sep 2025 — Present
APB based GPIO Design and Verification: Designed a GPIO peripheral interfaced with the APB protocol and developed a UVMtestbench with custom agents to enforce strict protocol validation.AXI VIP: Simulated AXI Master-Slave communication protocols and implemented a custom scoreboard forautomated result comparison.
Education
University Institute of Technology, The University of Burdwan
Bachelor of Engineering - BE, Electronics and Communication Engineering
Byabattarhat Adarsha High school
Higher Secondary, Science
Ichhapur Panchagrami High School
Secondary
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