Maelona Maxim Vas
Analog Layout Design Engineer @onsemi
Bengaluru, KA, IN
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WORK HISTORY
Jul 2024 — Present
Analog Layout Design Engineer @onsemi
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Bengaluru, IN
Part of the Layout Design Team for Analog and Mixed Signal Group at ON Semiconductor Technology working on Gate drivers, Smart FET, E-fuse and Power management ICs. Currently working on 250nm, 180nm and 65nm technology nodes to design layouts for multiple IPs.
EDUCATION
2020 — 2024
The National Institute Of Engineering, Mysore
Bachelor of Engineering - BE, Electronics and Communications
ABOUT MAELONA MAXIM VAS
Analog Layout Design Engineer at onsemi | Layout Design Intern at Texas Instruments | Research Intern at IISC
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