Madhuri Atluri

Senior Cad Engineer Circuit Simulation Design Automation @Intel

San Jose, CA, US
MOBILE NUMBERS
+14•••••••03

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WORK HISTORY

Dec 2015 — Present

Senior Cad Engineer Circuit Simulation Design Automation @Intel

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San Jose, CA, US

Developing and driving next generation analog/mixed-signal Circuit Simulation flows for 10nm, 14nm, 16nm & 20nm chip projects. Leading the circuit simulation flow methodologies and deployment for quality and efficiency.Investigating, Benchmarking, Evaluating all the available features of different external and internal spice simulation tools/flows for accuracy, runtime, performance on a mixed variety of robust testcases from internal design teams.Engaging in strategic roadmap development with key EDA vendors & cross functional teams to support needed flow enhancements for simulators and flows in command line and ADE environment.Lead the Cosim methodolgy, setup, planning and support on designer issues from mixed signal verification of blocks for several projects.Provide designers with quality support and resolution of spice/spectre related issues from different types of analysis like AC, DC, TRAN, PSS & noise analysis, Loop Stability etc.Debugging critical Spectre/Spice simulator and licensing issues in the different upstream/downstream circuit simulation flows like noise, power and signal EM/IR, Monte Carlo, cosim, statistical aging. Mentoring and guiding junior team members and several designers across different projects to get to speed on working with different simulators, flow methodologies and setups based on their design requirements.Worked closely with extraction team to analyze different internal and external RC reduction methodologies on different design testcases to determine the best solution for internal teams, evaluated the pros and cons of using included SPF or OA extracted view methodologies in ADE post layout simulations for internal usage.Validating design testcases with new PDK models and simulator versions using simulation based regressions to identify any issues before pre-releasing them into the project resources.Worked on some aspects of ckt sim and RV related Flow development with Python and shell scripts

EDUCATION

2000

Andhra University

Bachelor's Degree, Electrical and Electronics Engineering

2002

Arizona State University

Master's Degree, Electrical and Computer Engineering

SKILLS

Erc FlowUnderstanding of Serdes Design and LayoutsPhysical Design Methodology, Planning and ImplementationSigemCadCircuit Simulation Cad FlowsDebuggingLanguages: Veriloga and Verilogams.Prime TimeWorking Knowledge of Sta TimingSynopsys VcsVlsiAsicElectrical Validation of Serial LinksGem/Assura Extraction and CalibrePower and Signal Ir/Em FlowsAsic Circuit DesignMixed Signal Functional VerificationNoise Flows20nm, 28nm Tsmc TechnologyLayout Extraction Simulations.Synospys Cosim SimulatorAnalog Circuit DesignSoftware: Unix, C, C++, Java, Staroffice, Excel Etc.Esand Erc Check FlowSignal IntegrityMicroprocessorsUnderstanding of Place & Route, Floor PlanningSocPdv/Lvs FlowsAnalog Simulation Tools: Opus, Virtuoso, Spice, Spectre, Xa, Nanosim, Smartspice

ABOUT MADHURI ATLURI

Self driven and motivated engineer with focus on mixed signal circuit simulation CAD support for designers and cross functional teams on several projects, in-house/external vendor Spice/Spectre simulator evaluation/benchmarking, engaging in strategic roadmap development with key EDA vendors and internal teams to support needed circuit simulation related flow enhancements and new customization\'s for command line and ADE environments, drive next generation simulation flows methodologies & implementation, regression testing with new simulator versions and pdk models, scripting for flow development, working with infrastructure team to install and release new simulator versions across different projects & resolving simulator based license issues for critical projects.Proven track record of background and experience in high speed SERDES mixed signal functional verification with cosim flow, power and signal EM/IR and noise analysis flows, verilogAMS modelling of analog blocks, post silicon validation and debug of high speed serial I/O and DDR links, analog circuit design, signal integrity spice simulations of I/O blocks with package and trace models, understanding of physical design ASIC flow.

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