Madhura Kulkarni
Soc Verification Engineer @Qualcomm
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WORK HISTORY
Soc Verification Engineer @Qualcomm
San Francisco, CA, US
Working on the functional verification of PCIE and I/O peripheral blocks in UVM – writing testcases, both random and directed for corner cases, checkers, BFMs, sequences, agents and monitors checks and improved simulations byimplementing backdoor memory access mechanism for multiple blocks.•Generated testcases for connectivity and debugged issues with designers. Automated the flow for test generation•Provided solution for end-to-end automation of coverage reporting using the IMC tool•SOC DV testbench architect for a couple of Cloud-AI chips. Handled SOC DV RTL bringup, test-planning, regression management, regression tracking and analysis, toggle coverage generation and analysis•Worked on simulation speed-up through a couple of verification methodology improvements and worked with vendors from Synopsys, Cadence and Mentor Graphics for tool speed-up for improvement in wall-clock time
EDUCATION
Cummins College Of Engineering
Bachelor of Engineering (B.E.), Electronics And Telecommunication
North Carolina State University
Master’s Degree, Electrical and Computer Engineering
ABOUT MADHURA KULKARNI
Graduate Student at North Carolina State University specializing in ASIC Design / Verfication and Computer Architecture. Graduating in May 2018 and looking for full-time positions in RTL Design, Verification and Computer Architecture.Skilled in ASIC Design flow from RTL Design to post Silicon signal integrity.Knowledge of Design Tools: Modelsim 10.3b, Cadence Virtuoso, Mentor Graphics Calibre, Syopsys Design Vision, Xilinx, Microwind.Programming Languages: C, C++, Java BasicsHardware Descriptive Language: VHDL, Verilog, System Verilog,UVM, Perl, PythonScripting Language: PythonOther: CosmoscopeI have completed my undergraduate studies from University of Pune in Electronics and Telecommunication.
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