Madeshwaran N
RTL design engineer at Altera, an Intel
- Role
- Ip Logic Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Madeshwaran N
RTL Design Engineer | SoC IP Development | CXL/PCIe | Micro-Architecture | Synthesis | Verification-Aware DesignExperienced RTL Design Engineer with 7+ years in architecting synthesizable digital designs, developing reusable IP blocks, and delivering timing-optimized RTL for complex SoC subsystems. Skilled in bridging specification to implementation across digital logic design, verification.Strong hands-on expertise in:• RTL design using SystemVerilog/Verilog• Micro-architecture planning and development• Protocol integration: CXL (PCIe Gen5), AXI, UART, I2C• Front-end quality checks: Lint, CDC, STA• Scripting (TCL, Perl) for automation and CI-ready design flows• Tools: Verdi, VCS, Vivado, Xcelium, SpyglassI have contributed to multiple end-to-end silicon projects, including:• LVDS tunneling using SERDES interfaces• CXL.io/cache/mem RTL integration and validation• IP block implementation for Ethernet-to-CXL bridges• Real-time imaging pipelines, embedded ventilator control, and motor control on FPGA platforms
Experience
Ip Logic Design Engineer
Dec 2022 — Present · Bengaluru, IN
Design and verification on LVDS, LTPI and FIFO IP.Creating the Regtest environment for LVDS, LTPI and FIFO HWTCL.Debugging the RTL
Education
Jerusalem College of Engineering - India
Bachelor of Engineering - BE, Electrical and Electronics Engineering
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