M. T Sharath
Design and verification trained Engineer Digital, Verilog, System verilog, UVM
- Role
- Sw App Cloud Tech Support Associate at Accenture
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About M. T Sharath
I am a passionate and detail-oriented VLSI Design and Verification engineer, recently trained at Maven Silicon, where I gained hands-on experience and a solid understanding of digital design and verification methodologies. During my training, I enhanced my expertise in industry-standard tools, SystemVerilog, UVM (Universal Verification Methodology), and assertion-based verification techniques. I successfully worked on real-time projects, which helped me strengthen my problem-solving skills and develop a deeper understanding of verification environments, functional coverage, and debugging complex designs. I am eager to contribute my skills to innovative semiconductor projects and collaborate with teams to deliver high-quality designs. Looking forward to exploring opportunities where I can grow and make an impact in the field of VLSI.
Experience
Sw App Cloud Tech Support Associate
Jul 2025 — Present · Bengaluru, IN
Education
Ballari Institute of Technology and Management
Bachelor of Engineering - BE
2020 — 2024
Visvesvaraya Technological University
Bachelor of Engineering - BE
2020 — 2024
Maven silicon
Advance VLSI Design and Verification Course
2024 — 2025
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