M. Kranthi Kiran

About M. Kranthi Kiran

Professional Exposure:Hand-on experience in RTL and ASIC/FPGA Synthesis Implementation using verilog/VHDL l.RTL Checks: LINT,CDC,Synthesis,STA,IO Constraints generation.Experience in digital front end design and interfacing with various digital modules.Good knowledge on protocol such as SPI,I2C,CDC,UART,Basic knowledge on AXI and APB.Skilled in Verilog, VHDL, basic understanding on systemverilog,FPGA, CDC, code coverage,Questasim, working Hands on exprinace in Synthesis tools Vivado,ISE from(Xilinx),intel Qurtus prime and lattice daimond and lattice radiant.on board debugging with chipscop ILA,SignalTap and reveal analyser

Experience

1. Senior Engineer

   Tech Mahindra

   Aug 2024 — Present · Bengaluru, IN

Education

• Vidya Jyothi Institute Of Technology

  M.tech, Student

  2015 — 2017