Luis Medina
Silicon Validation Engineer
- Role
- Silicon Validation Engineer at Hewlett Packard Enterprise
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Silicon Validation Engineer
Jun 2023 — Present · Austin, TX, US
Education
University of Southern California
Bachelors
Skills
- Linux
- Debugging
- Static Timing Analysis
- Unix
- Hardware
- Vhdl
- C
- Vlsi
- Testing
- Logic Bist
- Verilog
- Microprocessors
- System on a Chip (Soc)
- Computer Architecture
- Dft
- Logic Design
- Rtl Design
- Soc
- Processors
- Cmos
- Asic
- Application-Specific Integrated Circuits (Asic)
- Encounter Test
- Ic
- Semiconductors
- Tcl
- Shell Scripting
- Perl
- Functional Verification
- Embedded Systems
- Eda
- Hardware Architecture
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