Lokender Saini
DV@Google
- Role
- Senior Dv Engineer at Google
- Location
- West Delhi, DL, IN
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Lokender Saini
Design Verification engineer with 14 years of experience in Design Verification. Worked on mutiple IP/subsystem/Soc from Spec to Verification completion using System Verilog/UVM/C. Have exposure on industry standard protocols like PCIe, USB 3.0, and 802.11n/ac/ax/be(WiFi)
Experience
Senior Dv Engineer
Dec 2025 — Present · Bengaluru, IN
Education
YMCA University of Science and Technology
Bachelor of Technology (B.Tech.), Electronics and Communication Engineering
2007 — 2011
Skills
- Field-Programmable Gate Arrays (Fpga)
- Vlsi
- Application-Specific Integrated Circuits (Asic)
- C++
- Universal Verification Methodology (Uvm)
- Verilog
- Pcie
- Functional Verification
- Tcl
- Spi
- Usb
- Rtl Design
- Hardware Architecture
- Vhdl
- Ncsim
- Uvm
- Usb3.0
- Systemverilog
- Modelsim
- C
- Static Timing Analysis
- Fpga
- Asic
- Very-Large-Scale Integration (Vlsi)
- Debugging
- System Verilog
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