Lohitha Manya Dasari
Digital Design Engineer @Western Semiconductor
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WORK HISTORY
Digital Design Engineer @Western Semiconductor
Tempe, AZ, US
Currently developing the RTL code for an Interrupt Service Handler in a RISC-V 64- bit single-core processor, implementing and configuring the relevant CSRs for software, hardware and timer interrupts and exceptions• Devised SerDes architecture in accordance with JEDEC with 64b/66b encoding and decoding incorporating LFSR-based scrambler/descrambler and CRC-32 error checking• Created synthesizable RTL for PISO (DFF-based daisy chain) and SIPO (shift register) modules, achieving full protocol compliance through functional verification
ABOUT LOHITHA MANYA DASARI
ASIC Design Engineer with a strong focus on RTL and low-power design, specializing in…
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