Litesh Sajnani
- Role
- Pll Design Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Litesh Sajnani
Mixed Signal Engineer skilled in 1) Design of Hybrid/All-Digital PLLs, OpAmps, Custom…
Experience
Pll Design Engineer
Aug 2018 — Present
Custom Circuit Design and flows for Digital PLLs, STA, Jitter analysis, Analog circuit modeling and verification
Skills
- Verilog
- Digital Electronics
- Field Work
- Digital Circuit Design
- Logic Design
- Simulations
- Computer Architecture
- Electronics Hardware Design
- Amplifiers
- Asic
- System Verilog
- Cadence
- Rtl Design
- Eagle Pcb
- Analog Circuit Design
- Sram
- Vhdl
- Mixed Signal
- Hspice
- Ncsim
- Fpga
- Microprocessors
- Spectre
- Pspice
- High-Speed Digital Design
- Virtuoso
- Ic
- Matlab
- Eagle
- Pcb Design
- Circuit Design
- Gate Level Simulation
- Logic Synthesis
- Pll
- Simulink
- Spice
- Physical Design
- Rtl Coding
- Real Value Verilog Model
- Integrated Circuit Design
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