Vishwanath Linga

About Vishwanath Linga

Distinguished Technical Leader with more than two decades of of experience specializing in the architecture and front-end development of complex ASICs, SoCs, and IPs. With extensive experience in chip design and development, I specialize in front-end activities from specifications to silicon. My expertise includes IP/Sub-System/SoC integration, low power design (UPF-based), multi-clock designs, CDC, RTL design with Verilog, synthesis, verification, and both pre- and post-silicon validation. I have a strong background in debugging, particularly in RTL, synthesis, and chip bring-up, and have led engineers across various disciplines.I have successfully led multiple ASIC tapeouts across advanced technologies (from 4nm to 65nm) and have significant experience working with external IP vendors and third-party back-end service providers. I have managed large projects, including technical proposal preparation, resource estimation, schedule tracking, and customer interaction. Notably, I have served as Project/Program & Design Manager for 5 ASIC tapeouts and contributed to various IPs and ASICs. I have also developed several controllers, including DMA, USB, and I2C, for multiple chips and SoCs.My work spans a wide range of protocols (e.g, PCIe, USB, HDMI, I2C) and EDA tools (e.g, Synopsys, Cadence, Altera, Xilinx). I possess hands-on experience in FPGA and ASIC debugging, including compliance testing for USB 2.0 and PCIe. In addition, I have led teams in recruitment, training, and mentoring of engineers. Throughout my career, I have successfully delivered high-quality solutions in key projects, including the ARM Cortex A9 SoC for DRDO, HDMI bridge chip, H.264 encoder chip, and PCIe/USB-based products, consistently ensuring customer satisfaction and project success.

Experience

1. Senior Director

   Soctronics

   Jan 2025 — Present · Hyderabad, IN

Education

• The Institution of Electronics and Telecommunication Engineers

  B.Tech, Electronics and Telecommunications

  1994 — 1998

• University College of Engineering, Osmania University, Hyderabad, India

  Master's Degree, Digital Systems Engineering - VLSI

  1999 — 2000

Skills

• Rtl Design
• Asic
• Pcie
• Fpga
• Usb
• Static Timing Analysis
• Systemverilog
• I2c
• Amba Ahb
• Soc
• Logic Analyzer
• Logic Design
• Xilinx
• Eda
• Functional Verification
• Uart
• Arm
• Ic
• Vlsi
• Rtl Coding
• Ahb
• Debugging
• Mixed Signal
• Training/Mentoring
• Team Management
• Altera
• Project Management
• Open Verification Methodology
• Silicon Debug
• Low Power Design
• Timing Closure
• Behavioral Modeling
• Team Building
• Cross-Functional Team Leadership
• Team Leadership
• Project Planning
• Problem Solving
• Arm Cortex A9
• Project
• Xilinx Vivado