Liladhar B Patil

Digital IP | RTL Design | Intern – Samsung Semiconductor | M.Tech VLSI @ IIT Jammu | B.Engg. EC @ GEC Bharuch | High-Level Modeling to RTL Implementation

Role
Engineer Trainee at Samsung Semiconductor
Location
Surat, IN
LinkedIn followers
500 followers

About Liladhar B Patil

I am an M.Tech student in VLSI Design at IIT, driven by deep curiosity, self-discipline, and the belief that challenges build character. My academic journey has been self-financed and self-driven — not by choice, but by circumstance. I’ve independently managed both my undergraduate and postgraduate studies while balancing significant personal responsibilities, all of which have shaped me into a problem-solver who thrives under pressure. My core interests lie in ASIC/FPGA design, digital system architecture, and front-end design verification. I’ve also gained hands-on experience through project work and academic internships, and am currently focused on applying my skills to solve real-world hardware challenges. I believe in showing up with commitment, even when conditions are tough. I’m now seeking full-time roles or internships where I can contribute technically, grow as an engineer, and be part of meaningful innovation. Let’s connect — I’m always open to learning, collaboration, and mentoring conversations.

Experience

  1. Engineer Trainee

    Samsung Semiconductor

    Jan 2025 — Present · Bengaluru, IN

    As part of the Digital IP team at Samsung Semiconductor, I am actively involved in the quality control (QC) processes of IP components, ensuring compliance with stringent design standards and functional requirements. My responsibilities also include mapping high-level SystemC models to their corresponding RTL (Register Transfer Level) implementations, supporting design validation and functional verification.This role has enabled me to strengthen my understanding of digital design workflows, HLSEC Flow, IP integration, and the intricacies of hardware modeling—bridging abstract system-level designs with hardware-accurate RTL representations.

Education

  • Indian Institute of Technology Jammu

    Master of Technology - MTech

    2023 — 2025

  • Government engineering College Bharuch

    Bachelor of Engineering - BE

    2016 — 2020

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Liladhar B Patil — Engineer Trainee at Samsung Semiconductor in Surat, IN | Unifers