Likhitha Bendadi
Design Verification Trainee at Sumedha IT | Learning Verilog, SystemVerilog & UVM | Aspiring DV Engineer
- Role
- Design Verification Trainee Sumedha IT at Sumedha Institute Of Technology
- Location
- Khammam, TG, IN
- LinkedIn followers
- 500 followers
Experience
Design Verification Trainee Sumedha IT
Sumedha Institute Of Technology
Sep 2025 — Present · Hyderabad, IN
Currently learning Design Verification at Sumedha IT, focusing on:Verilog, SystemVerilog, UVMRTL design and verification flowAMBA APB protocol, FIFO, SRAMArbitration, packet decoder, LRM, PCLRBuilding a strong foundation in RTL design and functional verification to pursue DV internship opportunities soon.
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