Lijo Mathew

About Lijo Mathew

I am passionate about efficient execution, solving complex challenges, and implementing…

Experience

1. Soc Design Engineer

   Intel

   Oct 2018 — Present · Bengaluru, IN

   Timing & Power Signoff lead.Managed the subsystem-level timing convergence for high-speed designs, specifically focusing on the Processor tile. Actively participated in constraints development and helped in providing critical feedback.Was responsible for generating timing models to support a range of use cases defined and facilitated by the Quartus tool (catering to FPGAs).Played a crucial role in multiple silicon debug activities, providing valuable contributions in finding bugs & implementing ECO fixes.Was responsible for timing Convergence of Memory subsystem (DDR4/LPDDR4), the biggest Memory controller designed based out of Synopsys IP’s.Developed & Handled custom timing checks associated with DDR IP.Collaborated closely with the Architecture team to define workloads and use cases. Was responsible for meeting power targets through workload-based optimizations and implementing Power ECOs. Additionally, generated Power models to support various use cases.

Education

• Indian Institute of Science

  Master of Technology (MTech)

  2013 — 2015

• Vidya Jyothi Institute Of Technology

  Bachelor of Technology (BTech)

  2009 — 2013

Skills

• C++
• Engineering
• Electronics
• Verilog
• Microsoft Office
• Synopsys Primetime
• Embedded Systems
• Microcontrollers
• Vhdl
• Java
• C
• Programming
• Very-Large-Scale Integration (Vlsi)
• Microsoft Excel
• Linux
• Matlab