Lijo Thomas

About Lijo Thomas

DFT/DFD Pre-Silicon Verification Engineer with 6+ years of Pre-silicon domain and 2 years…

Experience

1. Dft Dfd Design Verification Engineer

   Intel

   Apr 2016 — Present

   Expertise in driving the execution of the DFT and DFD test plan, debug and coverage analysis. Worked extensively in the verification of JTAG/TAP, IJTAG, Boundary scan, STF(parallel port), SCAN, MBIST, IOBIST, Array freeze and Memory dump, Scandump, Trigger, LCP and several other debug features including VISA, Trace and crash flow. • Deep knowledge and experience in clock-domain crossing and low-power techniques • Expertise in constrained random test generation, SV assertions and coverage analysis • Advanced knowledge and experience in UVM methodology - writes uvm checkers/scoreboards/drivers/monitors as part of feature verification. Mentors a team in the execution of the test plan and debug of regression failures. • Proficient in System Verilog, C++ and Python. • Expertise in Emulation based verification (FPGA) for functional, DFT and debug features. Deep understanding of Emulation model-builds, fuse infrastructure, reset sequence bring up and debug fabric configuration • Expertise in waveform review and debug using Verdi. Good strike record in finding RTL, firmware and testbench bugs and closing with the stakeholders. Recognized and awarded several times with Department Recognition Awards. Expertise in developing and automating test generation flows. • Experience in working with server crash verification flows (Flows that gets triggered when a crash occurs and the debug strategies). • Works closely with Architecture and Design teams in driving and reviewing the debug specifications • Good understanding of several Intel firmware’s (uCode, pCode, ocode) • Collaborates the end-to-end validation of functional and debug test content in simulation and Emulation for HVM testing which includes the reset bring-up, configuration setup, generation of traces/triggers, routing of traces to DDR memory and the validation of memory content which helps in catching issues before being deployed on the tester by collaborating with cross-functional teams.

Education

• Cochin University of Science and Technology

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

• National Institute of Technology Calicut

  Master of Technology (M.Tech.), Microelectronics and VLSI Design

  2010 — 2012