Liji Joy
Junior Fpga Design Engineer @GMV
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WORK HISTORY
Junior Fpga Design Engineer @GMV
Nottingham, GB
Single-chip navigation signal generator design for satellite payloads using Zync Navigation signal generator prototype for Lunar Communication and Navigation Services (LCNS) payload in S-band* Development of a Real-Time LunaNet LANS Receiver for Augmented Forward Signal (AFS)
EDUCATION
Sahrdaya College of Engineering & Technology (Autonomous)
Bachelor of Technology - BTech, Electronics and Communication Engineering
SNHSS irinjalakuda
Biology/Biological Sciences, General
Little flower convent irinjalakuda
SSLC
S.C.M.S. School of Engineering Technology, Karukutty P.O., Ernakulam
Master of Technology - MTech, VLSI and Embedded System Engineering
ABOUT LIJI JOY
As a Junior FPGA Engineer at GMV, I design and implement single-chip navigation signal generators for satellite payloads using Zync RFSoC, a cutting-edge FPGA technology that integrates RF and digital processing. I have contributed to the prototype development for the Lunar Communication and Navigation Services (LCNS) payload in S-band, which aims to provide reliable and secure communication and navigation services for lunar exploration missions.I have a Master of Technology in VLSI and Embedded System Engineering and B.Tech in Electronics and Communication Engineering, where I gained a strong foundation in digital electronics, logic design, and microprocessors. I also completed an Advanced ASIC Verification Trainee course at Maven Silicon, and an Internship from SION Semiconductor where I learned about Verilog, System Verilog, UVM, and RISC V Processor. I am committed to staying up-to-date with the latest advancements in FPGA design and simulation tools to ensure that my work is always of the highest quality. I am excited to continue growing as an FPGA Engineer and tackling new challenges in the field.
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