Nghia Truong

About Nghia Truong

Currently working as a DFT Engineer. Misc. skills:Analog/Mixed-signal Design Tools: PSpice/ HSpice, Cadence OrCAD, Calibre DRC/LVS, Pyxis ICStation, ICStudio, Eldo.Hardware/ PCB: Eagle CAD, I2C, 1-wire protocol.Programming/Scripting Language: Perl, Tcl, Verilog, VHDL, C, C++, Data Structure, Matlab. Digital Design Tools: Synopsis VCS, Design Compiler (DC), PrimeTime, ModelSim Questa.DFT Tools: Mentor Graphics TessentShell, FastScan, TestKompress, IJTAG.FPGA: Xilinx XC9500 CPLD, Spartan-3 FPGA.ANALOG & MIXED SIGNAL DESIGN Single/multiple-stage operational amplifiers, Stability, and Compensation.Current Mirror. Biasing, Band-gap, Matching, Noise.Mixed-Signal IC Building Block (comparator, ADC, etc.)Analog/Mixed Signal Layout Techniques.IC Device Theory & Fabrication.Solid State Electronic Devices (Device Physics).DIGITAL DESIGN ASIC/ RTL designs: VLSI, RTL logic design in Verilog/ VHDL, simulation test benches and logic synthesis techniques.Microcomputer System Design: PCI architecture, computer architecture. Static Timing Analysis (STA)

Experience

1. Staff Dft Engineer

   Marvell Technology

   Nov 2020 — Present · Santa Clara County, CA, US

Education

• California State University-Sacramento

  Master's Degree, Analog/ Mixed-Signal & ASIC

  2009 — 2011

• University of Illinois Urbana-Champaign

  Bachelor of Science (B.S.), Electrical Engineering

  2004 — 2007

• CoderSchool (IT W21)

  Product Management Training, Product Management

  2019 — 2019

• Le Hong Phong Highschool

  High School

  1999 — 2001

Skills

• Vhdl
• Verilog
• Pspice
• Very-Large-Scale Integration (Vlsi)
• Fpga
• Asic
• Dft
• Mixed Signal
• Debugging
• Analog Circuit Design
• Field-Programmable Gate Arrays (Fpga)
• Matlab
• Vcs
• C
• Spice
• Testkompress
• Icstation
• Rtl Design
• Tcl
• Modelsim
• Logic Design
• C++
• Application-Specific Integrated Circuits (Asic)
• Eldo
• Perl
• Embedded Systems
• Integrated Circuits (Ic)
• Vlsi
• Amplifiers
• Atpg