Leena Putrevu
- Role
- Design Verification Engineer at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Sep 2014 — Present
Skills
- C
- X86 Assembly
- Questa
- Perl Script
- C++
- Static Timing Analysis
- Rtl Design
- Systemverilog
- Cadence Virtuoso
- Embedded Systems
- Customer Service
- Cadence
- C#
- Perl
- Digital Ic Design
- Project Management
- Debugging
- Xilinx Ise
- Microprocessors
- Engineering
- Simulink
- Soc
- Cadence Virtuoso Layout Editor
- Testing
- Python
- Algorithms
- Formal Verification
- Vlsi
- Electrical Engineering
- Modelsim
- Vhdl
- Low Power Systems
- Vivado
- Microsoft Office
- Asic
- Silicon Validation
- Computer Architecture
- Simulations
- Verilog
- Assembly Language
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