Leelavathi Sureddi

About Leelavathi Sureddi

Seeking a challenging position in VLSI Design Verification where my skills and experience will greatly enhance the company\'s success and my personal growth. Proficiency at understanding of new technical methodologies quickly and converting it into productive manner.Area of Interest- ASIC, FPGA and Verification Specialties Good understanding of SystemVerilog & UVM Test Bench flow. Developed SV – UVM TB Components with directed, random & constrained random approach. Test case generation and Test plan development. Code & Functional Coverage Analysis. Knowledge of Assertion Based Verification (ABV). Familiar with Object Oriented Programming. Experience with Verilog /VHDL Coding.SKILL HDL’s : Verilog & : Environment : Tools : QuestaSim (Mentor), systems : Linux, Windows

Experience

1. Internship

   Maven Silicon

   Oct 2014 — Present

   UART IP CORE design in verilog, which includes different moules like tranmitter,receiver,Baud generator,Wish bone interface, RS232, and modem.

Education

• Z.P.High school,A.koduru,visakhapatnam,AP

  Bachelor of Engineering (B.Eng.)

  2009 — 2012

Skills

• C++
• Coverage Driven Verification and Functional Coverage
• Creation of Asic Verification Environment
• Creating Sv Testbenches
• Matlab
• Spi
• Vlsi
• Modelsim
• Writing Rtl Models
• Asic
• Uvm
• One and Half Experiance in Yentra Controls Company as a Engineer in Matlab.
• Creating Uvm Based Testbenches.
• C
• Trained in Mavensilicon on"Asic Front End Design and Verification",
• Simvision
• Eda Tools-Xilinx Ise,Modelsim,Quistasim
• Integrated Circuit Design
• Verilog
• Asic Design Flow
• Perl