Lay Desai
Principal Design Engineer (Physical Design) at Cadence
- Role
- Principal Design Engineer at Cadence
- Location
- Pune Division, MH, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Lay Desai
Recent: Worked on all aspects of physical design (like Floor planning, Power planning,…
Experience
Principal Design Engineer
Jan 2019 — Present
Skills
- Xilinx Ise
- Vlsi
- Physical Design
- Xilinx
- Perl
- Tcl
- Testing
- I2c
- Verilog
- C
- Modelsim
- Vhdl
- Simulations
- Logic Design
- Cadence Virtuoso
- Debugging
- Static Timing Analysis
- Rtl Coding
- Cmos
- Uart
- Rtl Design
- Fpga
- Asic
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