Lakshmiprashanth A.
Principal Design Engineer at Cadence
- Role
- Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Lakshmiprashanth A.
Professional Experience:A highly motivated expert in Analog & Mixed-Signal Layout Design with over 13 years of experience, consistently driving high-performance projects from concept to tape-out. Possesses a proven ability to lead teams and deliver complex designs across diverse process nodes (2nm - 180nm) and foundries (TSMC, UMC, GF, Samsung).Specialties:* High-Speed SerDes: Extensive experience with designs up to 800GHz (8 lane) for DSP, automotive, and RF applications. Successfully led the tape-out of a 4nm 56GHz SerDes project (Project Artemis).* Full-Chip Integration: Proficient in floor-planning, placement, power routing, schematic-driven layout, and IP/block integration.* Advanced Layout Techniques: Expertise in FinFET layouts and EM/IR solutions.* Design Verification & Automation: Developed layout automation methodologies and scripts for various design tasks and verification processes.Experience Highlights:* Led a 12-member team on a 65nm MEMS project and a 6-member senior engineer team on the 4nm Artemis project, both for US clients.* Co-authored a joint layout paper on \"critical checks on analog layouts\" and developed a unique analog layout dummy filling methodology.* Demonstrated a strong track record in functional safety (ASIL-D) automotive projects.Tools & Languages:* Scripting: Perl, Caliber SVRF, Cadence SKILL, TCL/TK, Sed, Awk, CSH.* Layout Editors: Virtuoso, Encounter (Innovus), Milkyway, IC-Compiler.* DRC/LVS Tools: Caliber-DRC/LVS, Hercules, ICV-LVS, Cadence Pegasus.* Parasitic Extraction Tools: QRC (Cadence), StarRCXT (Synopsys).* Other Tools: Calibre Design REV, EM/IR tools (Voltusfi), Quantus Insight, ParagonDx.Key IPs/Blocks Developed:CTLE, Receiver front-end (termination), DDR pads, Clock distribution (14GHz Phase Interpolator), Bandgap reference, LDO, Voltage monitors, Temperature sensors, Current mirrors, PLL (LC tank and inverter-based VCO), Process monitors, Pad-Ring adapters, Input filters, High Precision PWM, ADC, VGA, Oscillators, Channel Multiplexers.Previous Employers:1. Analog Devices India Pvt Ltd2. LeadIC Design Pvt Ltd (as the first employee in a service startup)3. Cadence Design SystemsConsulting Engagements:1. Maxlinear Technologies (2 engagements)2. Global Foundry -> Avera Semi -> Marvel Semiconductor3. Qualcomm India4. Broadcom India5. Untether Canada6. SiTime USA & Netherlands7. Celestial USAOpen to connecting with fellow design enthusiasts and exploring new opportunities.
Experience
Principal Design Engineer
Aug 2023 — Present · Bengaluru, IN
SerDes Layout Design
Education
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech, Microelectronics
2018 — 2020
Mei Polytechnic
High School Diploma, Electrical, Electronics and Communications Engineering
2009 — 2012
R.V.S Kannada and English school
High School/Secondary Certificate Programs
2009
B. M. S. College of Engineering
Bachelor's degree, Electrical, Electronics and Communications Engineering
2014 — 2017
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