Lata Dalakoti
Timing Engineer, Physical Design
- Role
- Timing Engineer, Physical Design at Intel
- Location
- Tempe, AZ, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Lata Dalakoti
15+ Years of extensive experience in Design Implementation of mixed signal blocks as…
Experience
Timing Engineer, Physical Design
Apr 2024 — Present · Chandler, AZ, US
Education
Banasthali Vidyapith
M.tech
2005 — 2007
PDMCE
Electrical, Electronics and Communications Engineering
2001 — 2005
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