Lalit Singh
IP/SOC RTL Design Engineer | ARM | Compute Architecture | Previously at Qualcomm & Nokia
- Role
- Staff Design Engineer at Arm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Lalit Singh
Strong experience in clock architecture, SDC signoff, power analysis, and system-level…
Experience
Staff Design Engineer
Dec 2024 — Present · Bengaluru, IN
Understanding of compute subsystems mucro-architecture.Developed timing and design constraints for compute subsystem from scratch.Micro-architecture of clock controller cpuss
Education
Inderprastha Engineering College Ghaziabad
B. TECH
2012 — 2016
Skills
- System Verilog
- Verilog
- Vhdl
- Digital Designs
- C
- C++
- Rtl Design
- Dsp Fpga
- Xilinx Ise
- Modelsim
- Altera Quartus
- Microsoft Excel
- Field-Programmable Gate Arrays (Fpga)
- Microsoft Office
- Zynq 700 Architechure
- Vivado
- Timing Analysis
- Chip Scope
- Ddr
- Linux
- Ethernet/Ip
- Mpeg Standards
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